(1). Field of the Invention
This invention relates to semiconductor integrated circuit structures and to methods for manufacturing such integrated circuits wherein self-aligned transistor structures are formed.
(2). Description of the Prior Art
The self-aligned silicon gate field effect transistor process and resulting structure has been a standard in the industry for some time. The process involves growing an insulating layer over the semiconductor substrate and then forming a polysilicon layer thereover. Lithography and etching techniques are used to remove all of the polysilicon layer except in the areas where the field effect transistor gates are to be located in the integrated circuit structure. This resulting gate structure is now used as a mask for forming the source/drain of the transistor in what is termed a self-aligned structure.
Improvements have been made in the self-aligned processing and structures. These improvements are particularly important in the manufacture of submicron integrated circuits.
One such improvement field has been for methods to form narrow dimensioned, for example, submicron regions on a semiconductor body. Reference is made to the I. T. Ho et al U.S. Pat. Nos. 4,209,349 and 4,209,350, K. Riseman U.S. Pat. No. 4,234,362 and the H. B. Pogge U.S. Pat. No. 4,256,514 which describe the formation of such regions. These patents all involve the formation of substantially horizontal surfaces and substantially vertical surfaces on a silicon body and then forming a layer of a very narrow dimension on both the substantially horizontal and substantially vertical surfaces. This layer is then subjected to an anisotropic etching process such as by reactive ion etching, to substantially remove the horizontal layer, exposing the bare silicon substrate, while leaving the vertical layer substantially intact. The vertical layer dimension is adjusted depending upon the original thickness of the layer applied. In this way such a narrow dimension region of one micrometer or less is obtained.
Another improved self-aligned gate structure is the lightly doped drain or LDD. For example, where the LDD in an N channel MOS FET is included, in addition to the channel separating implanted N+ source and drain regions, there are submicron diffused N- regions. These N- regions increase the channel breakdown voltage and reduce drain junction electron impact ionization (and thus, hot electron emission) by spreading the high electric field at the drain pinch-off region into the N- region. One improved process for making such an LDD device is described in the S. Ogura et al U.S. Pat. No. 4,366,613 in which the N- region is first formed using the polysilicon gate as the mask, submicron sidewall spacers are formed on the sides of the polysilicon gate, and the N+ source/drain regions are formed by ion implantation using the gate and sidewall spacer structure as the mask which results in the N- LDD structure. Other lightly doped drain structures and methods are shown by the I. T. Ho et al U.S. Pat. Nos. 4,209,349 and 4,209,350.
The reverse self-aligned field effect transistor process has been suggested by a limited number of workers in the field. Reference is made to the U.S. Pat. Nos. 4,296,426 to Thomson C. S. F., 4,378,627 to C. G. Jambotkar, 4,419,810 to J. Riseman and 4,546,535 to Shepard. These patents generally describe the reverse process wherein a heavily doped conductive layer such as polycrystalline silicon or the like is formed upon a silicon substrate and an insulator layer formed thereover. This multilayer structure is etched through to the bare silicon substrate to result in a patterned conductive polycrystalline layer or the like with substantially vertical sidewalls. The pattern of the conductive layer is chosen to be located above the planned source/drain regions with openings in the pattern at the location of the field effect transistor's channel. A sidewall insulator spacer can now be formed on the vertical sidewalls as described, for example in the previous paragraphs. The sidewall layer may be doped with conductive imparting impurities. The gate dielectric is formed on the channel surface. The source/drain region and preferably lightly doped region are simultaneously formed by thermal drive-in from the conductive first polycrystalline silicon layer or the like and insulator sidewall layer respectively. The desired gate electrode is formed upon the gate dielectric and electrical connections made to the various elements of the field effect transistor devices.
The methods described above for forming the self-aligned devices can lead to damage in the critical area of the substrate surface above the device channel, due to the difficulty in preventing etching materials from attacking the bare substrate. In the anisotropic ion etch to form sidewall spacers, and in the etch of the heavily doped conductive layer in the reverse self-aligned techniques, it is a difficult control problem to stop the etch at the proper time without damaging the substrate. One solution to remedy this problem in the formation of bipolar transistors is shown in U.S. Pat. No. 5,162,245 by Favreau. However, the selective polysilicon growth technique taught by Favreau may not be completely selective, with the result that polysilicon or polysilicon residues form on top of oxide 18. This unwanted polysilicon can cause later problems of defects, electrical shorts, etc.